At present, image coding methods such as MPEG1, MPEG2, MPEG4, H. 261, and H.263 are standardized as the International Standards.
FIG. 14 is a block diagram illustrating a structure of an image processing system based on these standards.
In the figure, reference numeral 1 denotes an encoder and numeral 9 denotes a decoder. The encoder 1 comprises an input circuit 2, a discrete cosine transform circuit 3, a quantization circuit 4, a variable-length coding circuit 5, and a bitstream transmitting circuit 6. The decoder 9 comprises a bitstream receiving circuit 10, a variable-length decoding circuit 11, an inverse quantization circuit 12, an inverse discrete cosine transform circuit 13, and an output circuit 14.
In the image processing system constructed as above, in the encoder 1, an image data is initially input from the input circuit 2, the input image data is cosine-transformed by the discrete cosine transform circuit 3, then quantized, and variable-length coded by the variable-length coding circuit 5, to obtain a code of various code length. Then, this code and a code length 7 are output to the bitstream transmitting circuit 6. In the bitstream transmitting circuit 6, the code is subjected to multiplexing using the code length 7 to obtain a bitstream 8 and the bitstream 8 is output to the decoder 9.
In the decoder 9, this output bitstream 8 is received by the bitstream receiving circuit 10, and variable-length decoded and demultiplexed using a code length 16 to obtain an original code 15, by a cooperative operation of the bitstream receiving circuit 10 and the variable-length decoding circuit. This decoded and demultiplexed code 15 is inverse-quantized by the inverse quantization circuit 12 and inverse-discrete-cosine-transformed by the inverse discrete cosine transformation circuit 13 to reproduce an original image data, and the original image data is output from the output circuit 14 to outside.
The multiplexing processing in the bitstream transmitting circuit 6 and the demultiplexing processing in the bitstream receiving circuit 10 are performed by special use arithmetic units or performed by software.
FIGS. 9(a) to 9(c) are diagrams schematically illustrating the multiplexing processing by the prior art software. FIG. 9(a) is a diagram showing masking processing for data of processing unit, which data includes a code in a certain order. FIG. 9(b) is a diagram showing shifting processing for data of processing unit, which data includes a code in a next order. FIG. 9(c) is a diagram showing multiplexing processing for the code in the next order into the code in the certain order.
In FIG. 9(a), numeral 901 denotes an i-th word data including a code(i) having a code length (bit length) of mi bits. LSB designates a Least Significant Bit and MSB designates a Most Significant Bit, respectively. When a variable-length code is to be subjected to multiplexing, the processing is performed using data of a prescribed bit length, including the variable-length code. This i-th word data represents data of processing unit which is used in that way. In addition, the i-th word data 901 has the code(i) at the end on the MSB side to process the i-th word data from the MSB side.
To perform the multiplexing processing, initially, a masking data 902 which has the same bit length as that of the i-th word data 901 and has “1” values in bits of a part corresponding to the code(i) and “0” values in bits of the other part, is generated.
Then, an OR operation of the generated masking data 902 and the i-th word data 901 is performed, and thereby-the masking processing to the i-th word data 901 for making values of bits except the code(i) “0” is performed (903).
Then, as shown in FIG. 9(b), an i+1-th word data 904, which is a processing unit data in the order subsequent to the i-th word data 901 and includes a code(i+1) having a mi+1-bit code length, is logically shifted rightward (in a direction from MSB to LSB) by mi bits which correspond to the bit length of the code(i), thereby moving the code(i+1) into a multiplexing position. Consequently, the i+1-th word data 904 becomes data having “0” values in bits from the end on the MSB side to an mi-th bit and having the code(i+1) in bits subsequent to the mi-th bit (905).
Then, as shown in FIG. 9(c), an OR operation of the i-th word data 903 which is subjected to the masking processing and the i+1-th word data 905 which is subjected to the rightward shifting processing is performed, thereby obtaining data 906 comprising the code(i) being multiplexed with the code(i+1) which is the code in the next order.
By performing the above-described processings successively, a bitstream is generated by successively multiplexing codes which are successively input.
FIGS. 10(a) to 10(c) are diagrams schematically illustrating the prior art demultiplexing processing by software. FIG. 10(a) is a diagram which shows processing of extracting a code in a certain order from a processing unit data. FIG. 10(b) is a diagram which shows shifting processing for a code of a next processing unit data. FIG. 10(c) is a diagram which shows data supplementation for the processing unit data after the code is extracted, from the next processing unit data.
In FIG. 10(a), numeral 911 denotes a j-th word data comprising a code(i) having a mi-bit code length, a code(i+1) having a mi+1-bit code length, and a code(i+2)′ having a mi+2′-bit code length. When the demultiplexing processing is to be performed for a multiplexed code, an input bitstream is temporarily received by an input register, and then processed in a unit of the received bitstream, i.e., in a unit of the bit number of the input register. This j-th word data 911 represents such a processing unit data of a bitstream. In the j-th word data 911, it is assumed that decoding processing is finished for the code(i), and that the code(i+1) is to be decoded next.
To perform this demultiplexing processing, initially, this j-th word data 911 is logically shifted leftward (in a direction from LSB to MSB) by mi bits which correspond to the bit length of the code(i), thereby extracting the code(i). Consequently, the j-th word data has the code(i+1) and the code(i+2)′ in this order in a part of bits from the end on the MSB side to the mi+1+mi+2′-th bit, and has values of “0” in bits of the other part (912).
Then, as shown in FIG. 10(b), a j+1-th word data, which is the next processing unit data and comprises a code(i+2)″ having a mi+2″-bit code length and a code(i+3) having a mi+3-bit code length, is logically shifted rightward by mi+1+mi+2′ bits. Thereby, the j+1-th word data becomes data having “0” values in bits from the end on the MSB side to the mi+1+mi+2′-th bit, and having the code(i+2)″ and a part of the code(i+3) in bits of the other part (914).
Then, as shown in FIG. 10(c), an OR operation of the j-th word data 912 which is subjected to the leftward shifting processing and the j+1-th word data 914 which is subjected to the rightward shifting processing, is performed, thereby obtaining data 914 comprising a part of empty bits generated by extracting the code(i) from the j-th word data 911 being supplemented with a part of the j+1-th word data 915.
By performing above-described processings successively, codes are successively subjected to demultiplexing from the bitstreams which are successively input.
In the above description, descriptions of a process for generating a masking data and a shift value setting and the like, are omitted.
However, the above-described prior art image processing system has the following drawbacks.
The image processing system using MPEG2 image coding method generally requires real time processing, deals with a large quantity of image data, and further has a large market scale. Therefore, a special use arithmetic unit (hardware) enabling high-speed arithmetic processing is used for the multiplexing processing for codes and the demultipliexing processing for codes.
On the other hand, the image processing systems using the image coding methods such as MPEG1, MPEG4, H.261, and H.263 do not have as large a market scale. Therefore, when a special use arithmetic unit is used for the multiplexing processing for codes and the demultiplexing processing for codes, there may be an increase in constraints on cost or availability for constituting the image processing system. On the other hand, when software is employed, plural steps are required for processing data as described with reference to FIGS. 9(a), 9(b), 10(a), and 10(b), whereby there arises an increase in the processing time and difficulty in performing the real time processing.
The present invention is made to solve the problems, and it is an objet of the present invention to provide an arithmetic unit able to perform the multiplexing processing for codes and the demultiplexing processing for codes at high speeds and which thereby has versatility.